AI-native IC design platform
From spec to silicon, orchestrated by AI.
Kilby Semi unifies all nine phases of chip design — from a natural-language spec to tapeout-ready GDSII. AI is applied surgically, only where it beats deterministic methods; foundry-proven tools run everything physics demands.
The pipeline
Nine phases, one orchestrator.
Every phase is idempotent and gated — no stage proceeds until its validation passes. Select a phase to inspect its purpose, artifacts, and gate.
AI strategy
AI where it wins. Determinism where it must.
Kilby refuses the all-AI trap. Generation and interpretation lean on models; mathematical correctness and physical accuracy stay with proven engines.
- Spec interpretation & feasibility
- Architecture suggestion
- RTL generation
- Verification planning
- Coverage-driven test generation
- Bug triage & timing-closure assist
- Logic synthesis
- Physical design & routing
- DRC / LVS signoff
- Static timing analysis
- ATPG & formal verification
- GDSII generation
If the task needs mathematical correctness or physical accuracy, it's deterministic. If it needs interpretation, generation, or exploration, it's AI.
Platform
Engineered like the silicon it ships.
Spec-to-silicon orchestration
One orchestrator drives all nine phases. Hand it a spec; it manages the path to a tapeout-ready final.gds.
Mandatory validation gates
No phase advances until its gate passes — lint, timing, coverage, DRC, LVS. Silicon has no undo.
Versioned, hash-traced artifacts
Every output is tagged with a SHA-256 and lineage. Reproducible, auditable, drift-detectable by construction.
First-class iteration
A timing miss in physical design re-spins synthesis automatically. Closed-loop feedback, not a one-shot pass.
Tool-agnostic interfaces
Standard formats — Verilog, SDC, DEF, GDSII, JSON — not proprietary APIs. Swap engines without rewrites.
Idempotent & structured
Same inputs, same outputs. Structured JSON logging throughout — every decision is inspectable, never a print().
Why Kilby Semi
Industry-standard always.
No proprietary shortcuts.
Foundry-proven, zero-compromise
Built around IEEE, UVM, SDC, UPF and GDSII — the formats foundries and signoff flows already trust.
AI applied surgically
Models accelerate the open-ended work; they never sit on the critical path of physical correctness.
Every gate is mandatory
Verification before done — lint, simulate, check logs. Correctness is proven, not assumed.
Root-cause discipline
No temporary patches. The platform finds the source of a failure and re-spins the right phase.
“Silicon has no undo. So every phase verifies before it commits, and every artifact can be traced back to the spec that demanded it.”
// Kilby Semi engineering principle
The next frontier:
quantum chip design.
The same disciplined, gated orchestration that takes a classical spec to GDSII extends naturally beyond CMOS. Kilby Semi is building toward quantum processor design — applying spec-driven planning, modeling, and signoff to qubit systems.
Classical IC / ASIC
Full spec-to-silicon flow across nine phases, in production.
Quantum-classical co-design
Control electronics and readout co-designed alongside the quantum layer.
Native qubit layout
Spec-driven planning & signoff for superconducting and spin-qubit devices.
Ecosystem
Standards-native. Tool-agnostic.
Open EDA engines // integrated
Deterministic phases run on a proven open-source signoff stack.
Standards & formats // native
Inputs and outputs every foundry flow already understands.
Get started
Compress your path from spec to tapeout.
See Kilby Semi run a real design end-to-end — from natural-language spec to signed-off GDSII.